1. Field of the Invention
The invention relates to interrupt routines in computer systems, and more particularly, to assertion of the proper interrupt starting address on an address bus when a system management interrupt is asserted.
2. Description of the Related Art
In the early years of personal computers, the International Business Machines (IBM) PC computer dominated the field. The IBM PC enjoyed sensational success, for it was one of the first affordable yet reasonably powerful desktop computers. Eventually, the domination of the IBM PC became so widespread that the IBM PC set the standards for personal computer architecture, system design, and software.
The IBM PC used the Intel Corporation's 8088 microprocessor in its central processing unit (CPU), which employs a 20-bit address bus for accessing system memory and I/O devices. Because the IBM PC so thoroughly dominated the personal computer market, software vendors created an array of software for the 20-bit bus of the 8088 microprocessor and the 8086 microprocessor. Much of this software forms the foundation of modern software. Consequently, due to the early dominance of the 20-bit bus in the IBM PC and the ground-breaking software created for it, many basic applications in use today are based on a 20-bit address bus.
The next generation of extremely successful IBM personal computers was the IBM PC/AT. To provide access to a wider range of memory and I/O devices, the IBM PC/AT architecture incorporated a 24-bit bus. At the heart of the IBM PC/AT was the Intel Corporation 80286 microprocessor, which utilizes a 24-bit address bus. Although the 24-bit addressing capability of the 286 microprocessor could drive the PC/AT's 24-bit bus, a standard 24-bit configuration was incompatible with certain of the software that had been developed for the 20-bit 8088 microprocessor. This was partially because the 8088 instruction register, when it reaches its limit of FFFFFh, rolls over to an initial value of 00000h. Thus, the memory space for an 8088 system can be viewed as continuous from the upper limit (FFFFFh) of the 20-bit address bus to the initial value (00000h). A 24-bit counter, however, generates a value of 100000h after 0FFFFFh, and does not roll over. Because some programs rely on the rollover characteristic, these programs are not compatible with a 24-bit address bus which continues to increment.
To maintain compatibility, an address bit 20 mask signal was incorporated into the computer system to simulate the rollover of the 8088 counter. Although several names and logic senses are used to designate the address bit 20 mask signal, the signal is referred to as the FORCE A20 signal herein, which is the common designation for the signal. When asserted, the FORCE A20 signal causes bit 20 of the address bus (bit A20) to be masked so that bit 20 is held low at all times, regardless of the value generated by the microprocessor. The FORCE A20 signal is controlled by a register that may be written by software. By driving bit A20 low, the FORCE A20 signal causes the address value asserted on the bus to simulate the rollover of the 8088 microprocessor. For example, when a 24-bit counter reaches the value 0FFFFFh, the next increment causes the counter value to become 1000000h. Consequently, the next address accessed would be 100000h, not 000000h which is accessed in an 8088 microprocessor system. When the FORCE A20 signal is asserted, however, bit A20 of the address bus is driven low. As a result, the value asserted on the address bus is 000000h, which is the proper value required to simulate the rollover of the 8088 instruction register.
Another significant development in personal computer systems is the system management interrupt (SMI). Originally, SMIs were power management interrupts devised by Intel Corporation for portable systems. Portable computers often draw power from batteries which provide a limited amount of energy. To maximize battery life, an SMI is asserted to turn off or reduce the power to any system component that is not currently in use. Although originally meant for laptop models, SMIs have become popular for desktop and other stationary models as well, and for purposes other than power management.
SMIs are asserted by either an SMI timer, by a system request or by other means. An SMI is a non-maskable interrupt having the highest priority in the system. When an SMI is asserted, an Intel microprocessor maps a portion of memory referred to as the system management memory (SMRAM) into the main memory space. The entire CPU state is then saved in the SMRAM in stack-like, last in/first out fashion. After the CPU state is saved, the microprocessor begins executing an SMI handler routine, which is an interrupt service routine to perform specific system management tasks, like reducing power to specific devices. While the routine is executed, other interrupt requests are not serviced, and are ignored until the interrupt routine is completed or the microprocessor is reset. When the SMI handler completes its task, the CPU state is retrieved from the SMRAM, and the main program continues.
In the first processors to use SMIs, the Intel Corporation 80386SL and 80486SL microprocessors, the SMRAM is mapped into the main memory space between 30000h and 3FFFFh. Data regarding the CPU state is stored starting at 3FFFFh going down like a conventional stack. After the CPU state is saved in the SMRAM, the microprocessor starts the SMI handler at memory address 38000h located in the SMRAM space. In the 80386 and 80486 microprocessor generations, the SMI start address is stored in a non-accessible register so that it cannot be changed by the programmer. Similarly, the use of the memory space between 30000h and 3FFFFh is preset into the microprocessor and unchangeable. Although this placement of the SMRAM and starting address is stable and known, it is often inconvenient. Any data stored in the main memory space between 30000h and 3FFFFh before the SMI is asserted is likely to be overwritten by the SMI handler and lost, unless hardware is developed which maps in special memory and maps out conventional memory. This mapping requirement has the problem of requiring extra logic and forces abrupt changes in memory contents necessitating flushing of any cache memory system. This has a cost and performance drawback. If the mapping is not performed, the software must be carefully designed around the memory space used by the SMRAM in order to prevent inadvertent loss of data.
To remedy this inconvenience, the latest generation of microprocessors from Intel Corporation, known as the Pentium or P5 microprocessors, permit the SMI handler starting address and the location of the SMRAM space to be changed by the user. Under the Pentium design, the SMI starting address stored in the microprocessor register is initially set to the conventional 30000h value. Consequently, when the first SMI is asserted, the SMI handler starts at address 38000h. While the SMI handler routine is executing, however, it may provide a different area of memory to be used as the SMRAM. This new SMRAM may start at any location in the main memory space chosen by the programmer. The SMRAM comprises a 64 kbyte block beginning at the new SMRAM start address. When the SMI handler finishes, the new starting address replaces the old starting address in the microprocessor's SMI starting address register.
When the next SMI is asserted, the microprocessor maps the new 64 kbyte block of memory into the main memory space as the SMRAM, and starts the SMI handler at the new starting address at the midpoint of the new SMRAM. For example, during the first SMI service routine, the programmer may change the SMRAM starting point from 030000h to 100000h. When the SMI is next asserted, the microprocessor maps the SMRAM into main memory space between 100000h and 10FFFFh. The microprocessor then references address 108000h for the SMI handler. This feature thus allows the programmer to choose a more convenient location in the main memory for the SMRAM.
Although the ability to relocate the SMRAM provides a convenient option to the programmer, it presents a problem for the computer architecture designer. As previously described, when the FORCE A20 signal is asserted, bit 20 of the address bus is driven low, regardless of the value asserted by the microprocessor. When an SMI is generated, the SMRAM is mapped into the main memory space designated by the programmer. If the 64 kbyte block of main memory is an odd Mbyte block instead of an even Mbyte block, bit 20 of the address bus must be driven high by the microprocessor. If the FORCE A20 signal is activated at the time the SMI is initiated, however, the FORCE A20 signal holds bit 20 of the address bus low. Consequently, the address value that is actually asserted on the bus is 1 Mbyte lower than the interrupt vector provided by the programmer. For example, if the start address chosen by the programmer is 308000h, the SMRAM should be mapped into the memory space between 300000h and 30FFFFh. If the FORCE A20 signal is asserted, however, bit 20 is held low, so that the address range actually provided to the main memory is 200000h to 20FFFFh, and the SMI handler starting address appearing on the bus is 208000h. The CPU state is then saved starting at 20FFFFh and going down, potentially overwriting important data stored in main memory. When the microprocessor obtains the new starting address, the address asserted is 208000h, which does not contain the SMI handler routine. Consequently, the system suffers an error and must be reset.
Because of this problem, a programmer choosing an SMRAM location in a conventional system is limited to only half of the potential main memory space in which to place the SMRAM. If the programmer inadvertently selects an SMRAM area within an odd Mbyte block of the main memory, important data may be overwritten and the system may suffer a failure. As a result, the flexibility provided to the programmer to select a convenient location for the SMRAM is limited to only half of the available memory space.